LVDS option
===========

As an option, the TX53 and TX6 are available with a dual LVDS and SATA interface instead of the parallel LCD interface.

In this case, the LCD interface signals LD0..LD19 are used to bring out the processor's LVDS interfaces. In addition, the TX53/TX6Q SATA interface is available on pins LD20..LD23. These pins are used for the USB3 high-speed signals on the TX8P.

LVDS pin mapping
-----------------

LVDS interface 0

+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+
| LCD_D  | 19    | 18    | 17    | 16    | 15    | 14    | 13    | 12    | 11    | 9     |
+========+=======+=======+=======+=======+=======+=======+=======+=======+=======+=======+
| Pin    | 137   | 136   | 135   | 134   | 133   | 132   | 131   | 130   | 128   | 126   |
+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+
| Signal | TX0_N | TX1_N | TX0_P | TX1_P | TX2_N | CLK_N | TX2_P | CLK_P | TX3_N | TX3_P |
+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+

LVDS interface 1

+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+
| LCD_D  | 10    | 8     | 7     | 6     | 5     | 4     | 3     | 2     | 1     | 0     |
+========+=======+=======+=======+=======+=======+=======+=======+=======+=======+=======+
| Pin    | 127   | 125   | 124   | 123   | 122   | 121   | 120   | 119   | 118   | 117   |
+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+
| Singal | CLK_P | CLK_N | TX0_P | TX3_P | TX0_N | TX3_N | TX1_P | TX2_P | TX1_N | TX2_N |
+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+

LVDS recommendations [1]_
----------------------------

Use the following recommendations for the LVDS.

* Follow standard high-speed differential routing rules for signal integrity.
* Each differential pair should be length matched to ± 5 mils.
* LVDS differential pairs should have a differential impedance of 100 Ω.

USB3 pin mapping (TX8P only)
-----------------------------------------

+--------+--------------+--------------+--------------+--------------+
| LCD_D  | 23           | 22           | 21           | 20           |
+========+==============+==============+==============+==============+
| Pin    | 141          | 140          | 139          | 138          |
+--------+--------------+--------------+--------------+--------------+
| Signal | USB_SS3_TX_P | USB_SS3_RX_P | USB_SS3_TX_N | USB_SS3_RX_N |
+--------+--------------+--------------+--------------+--------------+

SATA pin mapping (TX53, TX6Q, TX6QP only)
-----------------------------------------

+--------+----------+----------+----------+----------+
| LCD_D  | 23       | 22       | 21       | 20       |
+========+==========+==========+==========+==========+
| Pin    | 141      | 140      | 139      | 138      |
+--------+----------+----------+----------+----------+
| Signal | SATA_TXP | SATA_RXP | SATA_TXM | SATA_RXM |
+--------+----------+----------+----------+----------+

SATA recommendations [2]_
---------------------------

Use the following recommendations for the SATA.

* SATA differential pairs should have a differential impedance of 100 Ω.
* Each differential pair should be length matched to ± 5 mils.
* Follow standard high-speed differential routing rules for signal integrity.


.. [1] Freescale Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors, Chap. 2.10
.. [2] Freescale Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors, Chap. 2.9