3.18. 2nd Ethernet RMII (TX28 only)¶
| Pin | Signal | Description |
|---|---|---|
| 15 | RESET_B | Ethernet PHY reset. This signal is also connected to the TX28 onboard Ethernet PHY. |
| 101 | ENET_CLK | Ethernet PHY clock. This signal is also connected to the TX28 onboard PHY. This clock signal is split at the driver side on the TX28. The trace length on the baseboard should be about 35mm. |
| 152 | ENET1_RXD0 | Bit 0 of the 2 data bits that are sent by the transceiver on the receive path. |
| 153 | ENET1_RXD1 | Bit 1 of the 2 data bits that are sent by the transceiver on the receive path. |
| 154 | ENET1_TXD0 | Bit 0 of the MAC transmit data to the transceiver. |
| 155 | ENET1_TXD1 | Bit 1 of the MAC transmit data to the transceiver. |
| 156 | ENET1_TX_EN | Indicates that valid transmission data is present on TXD[1:0]. |
| 157 | ENET1_RX_EN | Receive Data Valid. |
| 197 | ENET_INT | Ethernet PHY interrupt. This signal is wired or with the TX28 onboard Ethernet PHY interrupt. |
| 198 | ENET_MDC | ENET_MDC |
| 199 | ENET_MDIO | ENET_MDIO |
