Display

Backlight and Display Control

Pin	Signal	type	I/O	Description
77	DISPEN	3V3	O	Display Enable
78	DISPBL	3V3	O	Display Backlight Control (PWM)

18-bit RGB Display Interface

Note

Only available on QSMP

Pin	Signal	type	I/O	Remarks
53	LCD_DE	3V3	O
54	LCD_VSYNC	3V3	O
55	LCD_HSYNC	3V3	O
56	LCD_PCLK	3V3	O
57	LCD_R1	3V3	O
58	LCD_R2	3V3	O
59	LCD_R3	3V3	O
60	LCD_R4	3V3	O
61	LCD_R5	3V3	O
62	LCD_R6	3V3	O
63	LCD_R7	3V3	O
64	LCD_G2	3V3	O
65	LCD_G3	3V3	O
66	LCD_G4	3V3	O
67	LCD_G5	3V3	O
68	LCD_G6	3V3	O
69	LCD_G7	3V3	O
70	LCD_B1	3V3	O
71	LCD_B2	3V3	O
72	LCD_B3	3V3	O
73	LCD_B4	3V3	O
74	LCD_B5	3V3	O
75	LCD_B6	3V3	O
76	LCD_B7	3V3	O

MIPI DSI Display

Pin	Signal	Remarks
79	DSI_D3P	Not available on QSMP, which only supports 2 lanes Only 2 lanes available on QSRZ
80	DSI_D3N
81	DSI_D2P
82	DSI_D2N
83	DSI_D1P
84	DSI_D1N
85	DSI_D0P
86	DSI_D0N
87	DSI_CKP
88	DSI_CKN

MIPI-DSI Design Recommendations

Parameter	MIN	TYP	MAX
Operating Speed			1.5 GHz
Signal Trace Length			250 mm
Differential Pair Skew			1 ps
Lane Skew			10 ps
Differential Trace Impedance	85 Ω	100 Ω	115 Ω
Single-ended Trace Impedance		50 Ω

LVDS Display

Pin	Signal
79	LVDS_D3P
80	LVDS_D3N
81	LVDS_D2P
82	LVDS_D2N
83	LVDS_D1P
84	LVDS_D1N
85	LVDS_D0P
86	LVDS_D0N
87	LVDS_CKP
88	LVDS_CKN

LVDS Design Recommendations

Parameter	MIN	TYP	MAX
Operating Speed			800 MHz
Signal Trace Length			250 mm
Differential Pair Skew			1 ps
Lane Skew			10 ps
Differential Trace Impedance	85 Ω	100 Ω	115 Ω
Single-ended Trace Impedance		50 Ω

QS Standard Contact Group Index

Pins	Function	Pins	Function	Pins	Function	Pins	Function
1-4	SPI	5-10	I2C	11-14	CAN	15-18	SAI
19-35	Ethernet	36-42	SD Interface	43-48	USB	49-52	Power Supply, Reset and Boot mode
53-76	18-bit RGB Display Interface	77-78	Backlight and Display Control	53-72	Camera	79-88	MIPI DSI Display
89-96	UART	97-100	SPI	1A,75A,76A,100A	PCIe	25A,26A,50A,51A	USB3 Super Speed