PCIe

The i.MX 8M Mini and i.MX 8M Plus have one PCIE interface. There is a pair of pins with the name of PCIE _CLK_P/N. These pins are bi-directional which can either be used to feed 100 MHz reference clock to the PHY from external clock source, or to output an internal generated 100 MHz reference clock to PCIE connector or PCIE device. Note that the internal clock exhibits larger jitter than that from PCIE clock generator.

NXP recommends to use an appropriate external PCIe reference clock generator. The NXP EVK board design uses an IDT 9FGV0241device. However, NXP does not recommend one supplier over another, and does not suggest that this is the only clock generator supplier. The device used should support all the specs (jitter, accuracy, etc.)

Route PCIe TX/RX and reference clock signal pairs with 85 Ω differential impedance.

Pin

Signal

Requirements

75A

PCIE_TXN_P

It is recommended to use a 0.1 μF cap on both the PCIE_TXP and PCIE_TXN outputs.

76A

PCIE_TXN_M

100A

PCIE_RXN_P

PCIe specification compliance requires AC coupling at each transmitter. The receiver must be DC coupled.

1A

PCIE_RXN_M

74

PCIE_CLK_P

75

PCIE_CLK_N

PCIe Design Recommendations

Parameter

MIN

TYP

MAX

Operating Speed

4 GHz

Signal Trace Length

12 cm

Differential Pair Skew

1 ps

Differential Trace Impedance

73 Ω

85 Ω

97 Ω

Single-ended Trace Impedance

38 Ω

45 Ω

52 Ω

QS Standard Contact Group Index

Pins

Function

Pins

Function

Pins

Function

Pins

Function

1-4

SPI

5-10

I2C

11-14

CAN

15-18

SAI

19-35

Ethernet

36-42

SD Interface

43-48

USB

49-52

Power Supply, Reset and Boot mode

53-76

18-bit RGB Display Interface

77-78

Backlight and Display Control

53-72

Camera

79-88

MIPI DSI Display

89-96

UART

97-100

SPI

1A,75A,76A,100A

PCIe

25A,26A,50A,51A

USB3 Super Speed