3.8. CSPI - Configurable Serial Peripheral Interface

Pin	Signal	Description	type	I/O
44	CSPI_SS0	Slave Select bidirectional, selectable polarity signal, output in master mode, and input in slave mode.	VDDIO	I/O
45	CSPI_SS1		VDDIO	I/O
46	CSPI_MOSI	Master Out Slave In bidirectional signal, which is TxD output signal from the data shift register in master mode. In Slave mode it is RxD input to the data shift register.	VDDIO	I/O
47	CSPI_MISO	Master In Slave Out bidirectional signal, which is RxD input signal to the data shift register in master mode. In Slave mode it is TxD output from the data shift register.	VDDIO	I/O
48	CSPI_SCLK	CSPI Clock bidirectional signal, which is CSPI clock output in master mode. In slave mode it is an input CSPI clock signal.	VDDIO	I/O
49	CSPI_RDY	Serial Data Ready signal - This input signal is used for hardware control only in master mode. It indicates that external SPI slave is ready to receive data. It will edge or level trigger a CSPI burst if used. If the hardware control enabled, CSPI will transfer data only when external SPI slave is ready.	VDDIO	I/O

The i.MX processors contains Configurable Serial Peripheral Interface (CSPI) modules that allow rapid data communication with fewer software interrupts than conventional serial communications. Each CSPI is equipped with two data FIFOs and is a master/slave configurable serial peripheral interface module, allowing processor to interface with both external SPI master and slave devices.