3.18. PCI express¶
|166||CLK1_P||Alternate reference clock for PCIe||LVDS||I/O|
|167||PCIE_RXM||PCI Express receive differential pair||LVDS||I|
|170||PCIE_TXM,||PCI Express transmit differential pair||LVDS||O|
The TX6 provides a ×1 PCIe lane. The PCIe module supports PCI Express Gen 2.0 interfaces at 5 Gb/s. It is also backwards compatible to Gen 1.1 interfaces at 2.5 Gb/s.
3.18.1. PCI Express interface recommendations ¶
188.8.131.52. PCI Express general routing guidelines¶
Use the following recommendations for PCI Express general routing:
- The trace width and spacing of the lanes ×1 signals should be such that the differential impedance is 85 Ω ± 10%.
- Route traces over continuous planes (power and ground). Avoid split planes, plane slots, or anti-etch.
- Maintain the parallelism (skew matched) between differential signals; these traces should be the same overall length.
- Keep signals with traces as short as possible.
- Route signals with a minimum amount of corners. Use 45-degree turns instead of 90-degree turns.
- Do not create stubs or branches.
- Maintain symmetry of differential pair routing.
184.108.40.206. PCI Express coupling lane¶
All signals are directly connected on the TX6 module. Refer to the Freescale Hardware Development Guide for a guideline to couple the signals. Consult the PCISig documentation for detailed information.
3.18.2. PCIe recommendations ¶
|Termination is required on the differential clock lines. Connect two 49.9 Ω resistors, one between REFCLK- and GND, the other between REFCLK+ and GND. Alternately, Connect a 100 Ω resistor between REFCLK- and REFCLK+.||These termination resistors should be placed as close as possible to the receiver device inputs in case the chip LVDS clock outputs are used as the REFCLK source for the PCIe endpoint device.|
|||Freescale Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors, chap. 2-7|
|||Freescale Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors, Table 1-10|