Setup of eval kit for CM33 debugging

The document Release Note for RZ/G2L Multi-OS Package shows how to load and debug CM33 firmware with a with Segger J-Link connection.

This can be done in the same way with a TXRZ module mounted on a TX Mainboard7. There are two processor signals, that must be setup correctly to enable JTAG debugging:

Switches between normal operation and debug operation.
Switches between normal operation and boundary scan test model.

Operating Mode:

BSCANP DEBUGEN Operating mode
0 0 Normal operation
0 1 Debug operations
1 X Boundary scan test mode

The two signals can be controlled with the jumper field JP5-JTAGMODE on the TX Mainboard7:


To debug the Cortex®-M33 core via JTAG, the JP5 jumpers must be set in the following way:


The 10-pin haeder of the SEGGER J-Link adapter must be connected to the 20-pin JTAG header ST6 on the TX Mainboard7 with an appropriate adapter in the following way:

Segger J-Link mini MB7 JTAG ICE Interface Functionality
1 - VTref 1 - 3V3 IO voltage reference
2 - SWDIO/TMS 7 - TMS  
3 - GND 4-20 - GND  
4 - SWCLK/TCK 9 - TCK  
5 - GND 4-20 - GND  
6 - SWO/TDO 13 - TDO  
7 - NC   unused
8 - TDI 5 - TDI  
9 - NC   unused
10 - nRESET 15 SRESET# board reset